Run-Time Reconfigurable Implementation Of DSP Algorithms

Abstract

This paper describes the reconfigurable implementation of a digital filter in an FPGA device. The filter implemented is a Laplacian filter which is used in DSP and image processing applications. For an efficient FPGA implementation of the filter, distributed arithmetic techniques were used. For a run-time reconfigurable implementation, the JBits SDK were used, which allows partial reconfiguration of the Xilinx Virtex FPGA devices.