Mapping Large Combinational Circuits With K-Lut based FPGAS Using Homogenous Dominating Cones

Abstract

Partitioning is a technique of dividing a circuit or system into a collection of smaller blocks (sub-circuits) with roughly equal sizes targeting to minimize the number of interconnections between the blocks. Due to the limited mapping resource of k-LUT FPGAs, large combinational circuits partitioning is of practical importance for k-LUT based FPGA circuit implementation. In this paper is presented multilevel multi-resource partitioning algorithm for partitioning large combinational circuits in order to efficiently use existing and commercially available FPGAs packages.