Journal of Control Engineering and Applied Informatics
Delay Optimum And Area Optimal Mapping Of k-LUT Based FPGA Circuits
Abstract
The paper presents several improvements to our synthesis platform Xsynth that was developed
targeting advanced logic synthesis and technological mapping for k-LUT based FPGAs. Having
implemented an efficient exhaustive k-feasible cone generator it was targeted delay optimum mapping
and optimal area. Implemented algorithm can use common unit-delay model and, the more general, the
edge-delay model. The last model allows arbitrary delay values assignments to each branch of a circuit
net. Such arbitrary delay values my reflect estimates of placement and routing delays. Powerful heuristics
targeting minimal area (number of used LUTs in the mapped network) allow determinations of delay
minimum solutions but having low used area.
targeting advanced logic synthesis and technological mapping for k-LUT based FPGAs. Having
implemented an efficient exhaustive k-feasible cone generator it was targeted delay optimum mapping
and optimal area. Implemented algorithm can use common unit-delay model and, the more general, the
edge-delay model. The last model allows arbitrary delay values assignments to each branch of a circuit
net. Such arbitrary delay values my reflect estimates of placement and routing delays. Powerful heuristics
targeting minimal area (number of used LUTs in the mapped network) allow determinations of delay
minimum solutions but having low used area.