Modified Single-Phase Adaptive Transfer Delay Based Phase-Locked Loop with DC Offset Compensation

Abstract

The phase-locked loops (PLL) represent a major component in different types of grid-connected power conversion applications. The main function of the single-phase PLLs represents the input quadrature signal generation (QSG), which can be performed by various algorithms. In this paper, the modified adaptive transfer delay single-phase PLL (ATD-PLL), which includes the input signal DC offset compensation, is used for the synchronization with the single-phase input signal, and for the positive sequence component separation and synchronization in a case of a three-phase application. The small-signal ATD-PLL dynamic analysis is performed, accompanied by a corresponding PLL parameter tuning procedure. The novel ATD-PLL performance is verified by simulation and experimental tests, proving its effectiveness, accuracy, and improved dynamic performance.