Optimizing Depth, Area and Dynamic Power of k-LUT Based FPGA Circuits

Abstract

This paper proposes an efficient algorithm for complex criteria applied to K-LUT based FPGA mapped circuits. This algorithm is developed considering an important design factor ? dynamic power consumption - in addition to other design factors that are traditionally considered. To increase performance, it was used a flexible mapping tool based on exhaustive generation of all K-bounded sub-circuits rooted in each node of the circuit. To achieve information about dissipated functional power was implement efficient simulator. Area is of paramount importance in FPGA mapping circuits. Lastly to lower power consumption, we devised several effective techniques designed for reducing area.