Run-Time Reconfigurable Implementation Of DSP Algorithms
- Authors
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Zoltan Baruch
Technical University of Cluj-Napoca, Computer Science Department
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- Abstract
- This paper describes the reconfigurable implementation of a digital filter in an FPGA device. The filter implemented is a Laplacian filter which is used in DSP and image processing applications. For an efficient FPGA implementation of the filter, distributed arithmetic techniques were used. For a run-time reconfigurable implementation, the JBits SDK were used, which allows partial reconfiguration of the Xilinx Virtex FPGA devices.
- References
- Published
- 2003-06-30
- Issue
- Vol. 5 No. 2 (2003)
- Section
- Articles