The Impact of Supply Voltage Reduction on The Static Noise Margins of a 6T-Sram Cell
- Authors
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E. I. Vatajelu
Universitat Politecnica de Catalunya, Electronic Engineering Department
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J. Figueras
Universitat Politecnica de Catalunya, Electronic Engineering Department
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- Abstract
- The power consumption, especially the leakage power, is a big issue in nanometric technologies. In scaled technologies, the impact of lowering the supply voltage in order to ensure the low leakage power, leads to a decrease in robustness. The paper investigates the effect of lowering the supply voltage on the robustness of a 6T SRAM cell, both in saturation and sub-threshold regimes. The Static Noise Margin (SNM) is evaluated analytically and compared with HSPICE simulations for 130nm, 90nm and 65nm Berkeley Predictive Technology Models (BPTM) [9]. Our results show that the SNM of the cell decreases nonlinearly with a linear decrease in the supply voltage. The proposed analytical model is also used to predict the minimum value of the supply voltage that preserves the data stored in a 6TSRAM cell, which is found to be approximatively 5% of the nominal value.
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- Published
- 2008-12-31
- Issue
- Vol. 10 No. 4 (2008)
- Section
- Articles