Delay Optimum And Area Optimal Mapping Of k-LUT Based FPGA Circuits
- Authors
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Ion I. Bucur
University Politehnica Bucharest, Faculty of Control and Computers
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Ioana Fagarasan
University Politehnica Bucharest, Faculty of Control and Computers
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Cornel Popescu
University Politehnica Bucharest, Faculty of Control and Computers
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George Culea
University of Bacau, Faculty of Electrical Engineering
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Alexandru E. Susu
Swiss Federal Institute of Technology Lausanne
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- Abstract
- The paper presents several improvements to our synthesis platform Xsynth that was developed targeting advanced logic synthesis and technological mapping for k-LUT based FPGAs. Having implemented an efficient exhaustive k-feasible cone generator it was targeted delay optimum mapping and optimal area. Implemented algorithm can use common unit-delay model and, the more general, the edge-delay model. The last model allows arbitrary delay values assignments to each branch of a circuit net. Such arbitrary delay values my reflect estimates of placement and routing delays. Powerful heuristics targeting minimal area (number of used LUTs in the mapped network) allow determinations of delay minimum solutions but having low used area.
- References
- Downloads
- Published
- 2009-03-30
- Issue
- Vol. 11 No. 1 (2009)
- Section
- Articles